Doped polysilicon is a commonly used gate electrode material in the construction of CMOS devices. The use of polysilicon is desirable insofar as it can be doped to achieve the desired work functions in the NMOS and PMOS gates. However, as CMOS devices are scaled to smaller dimensions, the use of polysilicon is attended by unacceptably high resistivities, reduced inversion charge densities, transconductance, and undesirable depletion of doped polysilicon gate electrodes, thus resulting in a detrimental increase in the thickness of the gate oxide layers. Problems also arise from dopant (e.g., boron) penetration by diffusion from the polysilicon into thin gate oxide layers.
As the equivalent gate oxide thickness (EOT) decreases below about 1.0 nm, the capacitance associated with the depletion layer in the polysilicon gate becomes an important limiting factor in EOT scaling. Hence, the use of a metal gate, and in particular, a dual metal gate, may be required when gate lengths of 50 nm or smaller are required. In a dual metal gate structure, an NMOS metal and a PMOS metal are used for the dual gates. However, current dual metal gate technology has unsolved problems in process integration.
The usual method for fabricating dual metal gate electrodes is to deposit the first metal on top of the gate dielectric, the later of which may be a high-k dielectric material. The first metal is then removed from one of the well regions, which may be the n-well or p-well region, using common lithographic and/or etch techniques. As a result, a portion of the gate dielectric is exposed in this region. The second metal is then deposited on top of the first metal and on the exposed portion of the gate dielectric. The first and second metals must be chosen carefully so that the two electrodes will exhibit the proper work functions. Unfortunately, even with the proper choice of metals, CMOS structures made by this process exhibit significant thermal stability issues.
There is thus a need in the art for a method for fabricating dual metal gate electrodes that overcomes the aforementioned problems. In particular, there is a need in the art for a method for fabricating CMOS structures and other devices having dual metal gate structures such that the resulting NMOS and PMOS gates will have the proper work functions and will exhibit appropriate thermal stability. These and other needs are met by the devices and methodologies described herein.